1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
Typical structures of conventional semiconductor chips includes a structure, in which an electrode provided on a semiconductor chip is connected to a terminal lead disposed in a periphery of a package via a wire bonding, and an encapsulating resin is employed to create a packaging thereof. Since reduced spacing between terminal leads due to increased number of terminals disposed in a semiconductor chip allow installing only limited number of elements in a substrate in the packaging having such structure, a problem of a difficulty in avoiding an increased size of the package for maintaining a required dimension of the spacing between the terminal leads is arisen. In order to solve such problem, a type of a chip including a bonding member employing a solder and a bump such as a package called a chip size package is proposed.
Typical compact package for a metal oxide semiconductor field effect transistor (MOSFET) includes a package described in U.S. Pat. No. 6,624,522. Such package is shown in FIG. 6. The package shown in FIG. 6 includes a U-shaped clip 45, a die 30 having a silicon body 31 and a contact post 36, and the clip 45 includes a web 48 having a plated inner surface 47 and legs 46. The silicon body 31 is coupled to an inner surface 47 via an electroconductive adhesive agent 60 so as to leave gaps 61 and 62 with the side surfaces of the legs 46 facing the side edges of the die 30.
U.S. Pat. No. 5,789,809 discloses a typical ball grid array (BGA) package for MOSFET. Japanese Patent Laid-Open No. 2000-21,914 and Japanese Patent Laid-Open No. H06-77,231 (1994) typically disclose semiconductor devices, which includes a passivating film, an under bump metal (UBM) and a gold (Au) bump that are provided on an aluminum (Al) pad, and is configured that the passivating film overlaps with the UBM and the Au bump. Japanese Patent Laid-Open No. 2000-299,343 discloses a semiconductor device, in which solder bumps are directly installed in a surface of a device to provide a coupling with a printed circuit board. Japanese Patent Laid-Open No. 2000-228,423 discloses a semiconductor device, comprising a metal post provided on an interconnect layer formed on a polyimide film, a barrier layer provided on the metal post and solder balls provided on the barrier layer.
In the conventional semiconductor device including the metal post typically disclosed in Japanese Patent Laid-Open No. 2000-228,423, an electrode provided on a semiconductor substrate 101 is coupled to an end of an electrode layer 107 formed on a polyimide film 113 and a metallic post 116 is formed in another end of the electrode layer 107, as shown in FIG. 5. In the semiconductor device disclosed in Japanese Patent Laid-Open No. 2000-228,423, the metal post 116 is formed via a columnar polyimide layer 113a and an electrode layer 114 for plating. Therefore, a polyimide layer is present under the metal post 116. A solder ball 118 is provided on the metal post 116 via the barrier layer 117.
When a semiconductor chip (Si) is flip-installed on a base substrate (organic material), differences in thermal expansion coefficient among the base substrate (organic material), solder (Sn) and the semiconductor chip (Si) cause thermal stresses in interfaces therebetween. When an interconnect layer is formed on a polyimide film and a metal post is further formed on the interconnect layer as disclosed in Japanese Patent Laid-Open No. 2000-228,423, the presence of the polyimide film reduces the stress. However, the MOSFET for power applications requires forming the UBM and the metal post on an aluminum (Al) interconnect (typically source pad) for achieving a miniaturization and an increased current capacity. In other words, the structure having the interconnect layer drawn on the polyimide film as disclosed in Japanese Patent Laid-Open No. 2000-228,423 is detrimental for both the miniaturization and the increase in the current capacity, and thus is not adopted. Results of the study by the present inventors show that, when the UBM and the copper (Cu) post are directly connected to the Al interconnect, an absence of a material such as a polyimide film that is capable of reducing the stress causes a propagation of thermal stresses created among the base substrate (organic material), solder (Sn) and the semiconductor chip (Si) without being relaxed, generating a crack in the Al interconnect, and the generated crack extends to the silicon material (Si).
For example, a thermal expansion coefficient of a copper (Cu) electroconductive cap is 17 ppm/degree C., that of a silicon semiconductor chip is 3 ppm/degree C., that of lead-free solder is 22 ppm/degree C., and that of a glass epoxy board (mother board) is 20 ppm/degree C. Larger difference in thermal expansion coefficient between the employed materials provides easier generation of cracks In addition, it is necessary to provide an improved life of a soldered joint. Thus, it is considered that an increased diameter of the Cu post or an increased height of the Cu post provide an effect for an enhanced life of the soldered joint. However, the present inventors have found a trend that such configuration would provide an increased stress in the coupling interface with the UBM and the Al interconnect.
Therefore, the present inventors consider providing further improved reliability in the bump coupling section.